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Diffstat (limited to 'academic/SimEng/README')
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diff --git a/academic/SimEng/README b/academic/SimEng/README new file mode 100644 index 0000000000..acc2230a48 --- /dev/null +++ b/academic/SimEng/README @@ -0,0 +1,28 @@ + SimEng is a framework for building modern, cycle-accurate processor +simulators. Its goals are to be: + + - Fast, typically 4-5X faster than gem5 + - Easy to use and modify to model desired microarchitecture + configurations. New cores can be configured in just a few hours + - Scalable, from simple scalar microarchitectures up to the most + sophisticated, superscalar, out-of-order designs + - Capable of supporting a wide range of instruction set + architectures (ISAs), starting with Armv8 but eventually including + RISC-V, x86, POWER, etc. + - Accurate, aiming for simulated cycle times being within 5-10% of + real hardware + - Open source, with a permissive license to enable collaboration + across academia and industry + + SimEng places an emphasis on performance and ease of use, whilst +maintaining a clean, modern, simple and well-documented code base. +For example, the current out-of-order (OoO) model is implemented +in around 10,000 lines of simple C++, with another 9,000 lines or +so implementing the specifics of the Armv8 ISA, and around 13,000 +lines of code in the accompanying test suite. SimEng should be +simple to read and understand, making it ideal to modify to your +requirements and include it in your projects. + + + Invocation example: + # simeng /usr/share/SimEng-0.9.4/configs/a64fx.yaml |