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+ DRAMsim3 models the timing paramaters and memory controller behavior
+for several DRAM protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5,
+GDDR6, HBM, HMC, STT-MRAM. It is implemented in C++ as an objected
+oriented model that includes a parameterized DRAM bank model, DRAM
+controllers, command queues and system-level interfaces to interact
+with a CPU simulator (GEM5, ZSim) or trace workloads. It is designed
+to be accurate, portable and parallel.