diff options
Diffstat (limited to 'system/xen/xsa/xsa260-1.patch')
| -rw-r--r-- | system/xen/xsa/xsa260-1.patch | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/system/xen/xsa/xsa260-1.patch b/system/xen/xsa/xsa260-1.patch new file mode 100644 index 0000000000..21da59cddd --- /dev/null +++ b/system/xen/xsa/xsa260-1.patch @@ -0,0 +1,72 @@ +From: Andrew Cooper <andrew.cooper3@citrix.com> +Subject: x86/traps: Fix %dr6 handing in #DB handler + +Most bits in %dr6 accumulate, rather than being set directly based on the +current source of #DB. Have the handler follow the manuals guidance, which +avoids leaking hypervisor debugging activities into guest context. + +This is part of XSA-260 / CVE-2018-8897. + +Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> +Reviewed-by: Jan Beulich <jbeulich@suse.com> + +--- a/xen/arch/x86/traps.c 2018-04-13 15:29:36.006747135 +0200 ++++ b/xen/arch/x86/traps.c 2018-04-13 15:44:57.015516185 +0200 +@@ -1761,11 +1761,36 @@ static void ler_enable(void) + + void do_debug(struct cpu_user_regs *regs) + { ++ unsigned long dr6; + struct vcpu *v = current; + ++ /* Stash dr6 as early as possible. */ ++ dr6 = read_debugreg(6); ++ + if ( debugger_trap_entry(TRAP_debug, regs) ) + return; + ++ /* ++ * At the time of writing (March 2018), on the subject of %dr6: ++ * ++ * The Intel manual says: ++ * Certain debug exceptions may clear bits 0-3. The remaining contents ++ * of the DR6 register are never cleared by the processor. To avoid ++ * confusion in identifying debug exceptions, debug handlers should ++ * clear the register (except bit 16, which they should set) before ++ * returning to the interrupted task. ++ * ++ * The AMD manual says: ++ * Bits 15:13 of the DR6 register are not cleared by the processor and ++ * must be cleared by software after the contents have been read. ++ * ++ * Some bits are reserved set, some are reserved clear, and some bits ++ * which were previously reserved set are reused and cleared by hardware. ++ * For future compatibility, reset to the default value, which will allow ++ * us to spot any bit being changed by hardware to its non-default value. ++ */ ++ write_debugreg(6, X86_DR6_DEFAULT); ++ + if ( !guest_mode(regs) ) + { + if ( regs->eflags & X86_EFLAGS_TF ) +@@ -1798,7 +1823,8 @@ void do_debug(struct cpu_user_regs *regs + } + + /* Save debug status register where guest OS can peek at it */ +- v->arch.debugreg[6] = read_debugreg(6); ++ v->arch.debugreg[6] |= (dr6 & ~X86_DR6_DEFAULT); ++ v->arch.debugreg[6] &= (dr6 | ~X86_DR6_DEFAULT); + + ler_enable(); + pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC); +--- a/xen/include/asm-x86/debugreg.h 2015-02-11 09:36:29.000000000 +0100 ++++ b/xen/include/asm-x86/debugreg.h 2018-04-13 15:44:57.015516185 +0200 +@@ -24,6 +24,8 @@ + #define DR_STATUS_RESERVED_ZERO (~0xffffeffful) /* Reserved, read as zero */ + #define DR_STATUS_RESERVED_ONE 0xffff0ff0ul /* Reserved, read as one */ + ++#define X86_DR6_DEFAULT 0xffff0ff0ul /* Default %dr6 value. */ ++ + /* Now define a bunch of things for manipulating the control register. + The top two bytes of the control register consist of 4 fields of 4 + bits - each field corresponds to one of the four debug registers, |